1. Technical Field
The present invention relates to circuit design and operation of circuits. More particularly, the present invention relates to synchronously transferring control signals in a clock distribution flow. Still more particularly, the present invention relates to transferring data between two different clock domains which are both derived from the same clocking source.
2. Description of Related Art
The clock signal for all memory storage elements on an electronic chip are generated centrally on the chip at the phase locked loop (PLL) and distributed to the memory storage elements through a series connection of wires and buffering circuits. These wires and buffering circuits present a delay element in the clock distribution path. The electrical wire delay is due to the natural parasitic inductive, resistive, and capacitive characteristics of the wire. The buffering circuit delay is generated by the devices within the buffering circuit. As the frequency of the chip is increased, the delay between the launch of a clock edge at the PLL and its arrival at the memory storage elements, can exceed the clock signal time period.
In order to stop the clock for either power dissipation control or debug control, a logic gate is introduced into the clock distribution path in series with the clock distribution wires, buffering circuits and PLL so that the clock signal distributed to the memory storage elements can be forced by the logic gate to either a logic xe2x80x981xe2x80x99 or logic xe2x80x980xe2x80x99 state for an indefinite period of time. The memory storage elements receiving the clock signal generate the control signal for this logic gate, which enables the logic gate to start or stop the clock signal.
It is important for the logic control signal, from the memory storage element, to arrive at the logic control gate while the clock signal logic level is at the desired stop or start logic level so as not to produce an improperly formed clock pulse. The arrival time of the logic control signal from the memory storage element is directly controlled by the delay of the clock distribution path. As that path delay varies, so will the logic control signal arrival time vary at the logic gate potentially causing incomplete clock pulses.
For example, FIGS. 1A-1D are exemplary illustrations of a typical clock distribution on a typical electronic chip. Electronic chips may contain logic and memory circuits as well as circuits to support these logic and memory circuits. FIG. 1 may consist of one or more electronic chips containing logic and memory circuits as well as circuits to support these logic and memory circuits. The logic and memory circuits may be interconnected in a manner to provide the expected operation of a processor, adapter, bridge or interface element (not shown). Located on these one or more electronic chips is a support circuit consisting of serially connected buffers and electrical wires which distribute a periodic clock signal from a centrally generated source to the memory circuits distributed throughout the electronic chip shown as circuit 100 in FIG. 1A.
In this example, PLL 102 provides clock signal 104 which is distributed throughout the electronic chip using buffering circuits and control circuits 106, 110, 114, 118, 124, 128, and 132 and interconnecting signals 108, 112, 116, 120, 126, 130, C1134, and C2136 to memory storage circuit 144. PLL output signal 104 provides a clock signal input to buffer circuit 106 which may consist of one or more series connected inverter circuits. Buffer circuit 106 may be an inverting or a logically non-inverting circuit. Buffer circuit 106 outputs clock signal 108 which is input to selector circuit 110. Selector circuit 110 may choose either signal 108 or signal 142 to output signal 112. For example, if selector signal 148 is at a logic low level (xe2x80x9c0xe2x80x9d), then selector circuit 110 outputs signal 112 based on clock signal 108. Otherwise, if selector signal 148 is a logic high level (xe2x80x9c1xe2x80x9d), then selector circuit 110 outputs signal 112 based on selector signal 142. In this example, selector signal 148 represents a logic low level (xe2x80x9c0xe2x80x9d). In other words, output signal 112 becomes the logical value of either clock signal 108 or signal 142 depending on the logical value of selector signal 148. If selector signal 148 is a logical low level, then output signal 112 is the logically equivalent to clock signal 108. If selector signal 148 is a logic high level, then output signal 112 is the logical equivalent of signal 142.
Signal 112 is input to buffer circuit 114 which outputs signal 116. Signal 116 is input to buffer circuit 118 and outputs signal 120. Signal 120 is input to buffer circuit 124 which outputs signal 126. Signal 126 is input to buffer circuit 128 which outputs signal 130. Buffer circuits 114, 118, 124 and 128 may be logically inverting or non-inverting circuits. Signal 130 is input to clock regenerator circuit 132 which outputs signals C1134 and C2136 to memory storage circuit 144. Memory storage circuit 144 consists of memory circuit 150 and memory circuit 152. Memory circuit 150 provides its stored signal 154 to memory circuit 152. Memory circuit 152 outputs signal 148.
Clock regenerator circuit 132 outputs signal C1134 to memory circuit 150 and provides signal C2136 to memory circuit 152. Clock regenerator circuit 132 provides a buffered logical inversion of signal 130 to output C1134 and provides a buffered logical equivalent of signal 130 to output C2136. Signal 158 provides input to memory storage circuit 144 which is transmitted to signal 148 through a sequential process controlled by C1134 and C2136.
Signal 158 provides input to memory circuit 150. When signal C1134 is a logical high level (xe2x80x9c1xe2x80x9d), memory circuit 150 outputs the logical value of signal 158 to stored signal 154, which is transmitted to memory circuit 152. When signal C1134 changes from a logical high level (xe2x80x9c1xe2x80x9d) to a logical low level (xe2x80x9c0xe2x80x9d), the logical value of signal 158 is stored in memory circuit 150 and outputs stored signal 154 to memory circuit 152. When C2136 changes from a logical low level (xe2x80x9c0xe2x80x9d) to a logical high level (xe2x80x9c1xe2x80x9d), memory circuit 152 outputs signal 154 to signal 148. When C2136 changes from a logical high level (xe2x80x9c1xe2x80x9d) to a logical low level (xe2x80x9c0xe2x80x9d), signal 154 is stored in memory circuit 152 and outputs signal 148 based on stored signal 154.
Further detailed description of memory storage circuit 144 and similar memory storage circuits may be found in, for example, E. B. Eichelberger and T. W. Williams, xe2x80x9cA Logic Design Structure for LSI Testabilityxe2x80x9d, IEEE proceedings of 14th Design Automation Conference, June, 1977, pp. 462-468 and Stephen H. Unger and Chung-Jen Tan, xe2x80x9cClocking Schemes for High-Speed Digital Systemsxe2x80x9d, IEEE Transactions on Computers, Vol C-35, No. 10, October 1986, pp. 180 to 195. Other similar clock distribution examples may be found in, for example, xe2x80x9cCircuits, Interconnections, and Packaging for VLSIxe2x80x9d, by Bakoglu, 1990, and IEEE Journal of Solid-State Circuits, Vol 30, No. 4, April 1995, xe2x80x9cA Wide-Bandwidth Low-Voltage PLL for PowerPC(trademark) Microprocessorsxe2x80x9d, by Jose Alvarez, et al, pg. 383, Section VII. In addition, PLL circuits are common in the industry and their functionality on a typical electronic chip for clock signal generation is described in, for example, IEEE Journal of Solid-State Circuits, Vol 27, No. 11, November 1992, xe2x80x9cA PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessorsxe2x80x9d, by Ian A. Young, et al, pg. 1599.
In the present description of the preferred embodiments, a logical high level may be considered a xe2x80x9c1xe2x80x9d, and a logical low level will be considered a xe2x80x9c0xe2x80x9d. The memory circuit 150 is considered the xe2x80x9cmasterxe2x80x9d, memory circuit 152 is considered the xe2x80x9cslavexe2x80x9d and memory storage circuit 144 is considered a master/slave flip-flop.
FIGS. 1B, 1C, and 1D are exemplary waveforms which illustrate the location of the launching and capturing latches when exhibiting typical process delays, slow process delays and fast process delays, respectively, produced by circuit 100. In FIGS. 1B, 1C and 1D, T is the period of the clock signal and xcfx84 (tau) is the clock distribution latency.
FIG. 1B represents the waveforms for various signals in circuit 100 of FIG. 1A for typical operating conditions. Waveform 108 represents clock signal 108 and consists of first rising edge 103 and first falling edge 101 and second rising edge 121 and second falling edge 123 and additional rising and falling edges, each occurring periodically with a delay T between each rising edge and an equivalent delay T between each falling edge where T is the clock period. Waveform 136 represents clock signal C2136 and consists of first rising edge 105 and first falling edge 117 followed by a logic low level 119 instead of the expected periodic clock pulses. Waveform 136 first rising edge 105 occurs xcfx84 time units after waveform 108 first rising edge 103 which places the waveform 136 first rising edge 105 occurring after the waveform 108 first falling edge 101 and before waveform 108 second rising edge 121. In FIG. 1B, xcfx84 is less than T.
Waveform 148 represents selector signal 148 and consists of first rising edge 111 occurring after waveform 136 first rising edge 105. Waveform 112 represents signal 112 provided by selector 110 and consists of first rising edge 107, first falling edge 109, followed by a logic low level 115 instead of the expected periodic clock pulses. Waveform 112 first rising edge 107 occurs after waveform 108 first rising edge 103, but before waveform 108 first falling edge 101. Waveform 112 first falling edge 109 occurs after waveform 108 first falling edge 101 but before waveform 108 second rising edge 121. Waveform 148 first rising edge 111 occurs after waveform 112 first falling edge 109 but before waveform 112 expected second rising edge and before waveform 108 second rising edge 121.
The process of stopping the clock is initiated by the clock signal 108 rising edge 103 which propagates through selector 110 to form signal 112 rising edge 107 which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 rising edge 105. In this example, selector signal 148 is a logic low level which causes selector 110 to provide signal 108 to output signal 112. Clock signal C2136 rising edge 105 causes storage circuit 144 to provide rising edge 111 for selector signal 148. Clock signal 108 first falling edge 101 propagates through selector 110 to form signal 112 falling edge 109 which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 falling edge 117. Selector signal 148 rising edge 111 occurs after clock signal 108 falling edge 101 but prior to clock signal 108 second rising edge 121 while clock signal 108 is a logic low level. Selector signal 148 logic high signal causes selector 110 to provide logic low level signal 142 to output signal 112 prior to clock signal 108 second rising edge 121. When clock signal 108 second rising edge 121 occurs, selector circuit 110 does not provide clock signal 108 to signal 112 due to the logic high level provided by selector signal 148. Signal 112 remains at a logic low level 115 instead of the expected periodic clock signal 108 second rising and falling edges 121 and 123, respectively. Signal 112 logic low level 115 keeps all clocks signals at a static logic level as represented by clock C2136 logic low level 119 instead of the expected periodic clock pulse from clock signal 108 second rising and falling edges 121 and 123, respectively.
FIG. 1C represents the waveforms for various signals in the circuit 100 of FIG. 1A for slow operating conditions. As in FIG. 1B, waveform 108 represents clock signal 108 and consists of a first rising edge 125 and a first falling edge 127 and additional rising and falling edges, each occurring periodically with a delay T between each rising edge and an equivalent delay T between each falling edge where T is the clock period. Waveform 136 represents clock signal C2136 and consists of a first rising edge 129 and a first falling edge, a second rising edge 139, a second falling edge 147 followed by a logic low level 151 instead of the expected periodic clock pulses. Waveform 136 first rising edge 129 occurs xcfx84 time units after waveform 108 first rising edge 125 which places the waveform 136 first rising edge 129 occurring after waveform 108 second rising edge and before waveform 108 second falling edge. In FIG. 1C, xcfx84 is greater than T.
Waveform 148 represents selector signal 148 and consists of first rising edge 131 occurring after waveform 136 first rising edge 129. Waveform 112 represents signal 112 provided by selector 110 and consists of first rising edge 133, a first falling edge, followed by a second rising edge 141, followed by a second falling edge 143, followed by a logic low level 149 instead of the expected periodic clock pulses. Waveform 112 first rising edge 133 occurs after waveform 108 first rising edge 125, but before waveform 108 second rising edge. Waveform 112 second rising edge 141 occurs after waveform 108 second rising edge but before first waveform second falling edge. Waveform 148 first rising edge 131 occurs after waveform 112 second rising edge 141 but before waveform 112 second falling edge 143 and before waveform 108 second falling edge.
The process of stopping the clock is initiated by clock signal 108 rising edge 125 which propagates through selector 110 to form signal 112 rising edge 133 which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 rising edge 129. Selector signal 148 is a logic low level which causes selector 110 to provide clock signal 108 to output signal 112. Clock signal C2136 rising edge 129 causes storage circuit 152 to provide rising edge 131 for selector signal 148. Clock signal 108 first falling edge 127 propagates through selector 110 to form signal 112 waveform 112 first falling edge which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 waveform 136 first falling edge. Clock signal 108 second rising edge propagates through selector 110 to form signal 112 waveform 112 second rising edge 141 which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 waveform 136 second rising edge 139. Selector signal 148 rising edge 131 occurs after clock signal 108 waveform 108 second rising edge but prior to clock signal 108 waveform 108 second falling edge while clock signal 108 is a logic high level. Selector signal 148 logic high signal causes selector 110 to provide logic low level signal 142 to output signal 112 forming waveform 112 second falling edge 143 prior to clock signal 108 waveform 108 second falling edge. As a result, the clock pulse on signal 112 waveform 112 second rising edge 141 and second falling edge 143 is smaller than the clock pulse provided by signal 108 waveform 108 second rising edge and second falling edge. Signal 112 waveform 112 second falling edge 143 continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 second waveform second falling edge 147. As a result, the clock pulse on signal 136 waveform 136 second rising edge 139 and second falling edge 147 is smaller than the clock pulse provided by signal 108 waveform 108 second rising edge and second falling edge. When clock signal 108 second falling edge occurs, selector circuit 110 does not provide clock signal 108 to signal 112 due to the logic high level provided by selector signal 148. Signal 112 remains at a logic low level 149 instead of expected periodic clock signal 108 third rising and falling edges. Signal 112 logic low level 149 keeps all clock signals at a static logic level as represented by clock C2136 logic low level 151 instead of the expected periodic clock pulse from clock signal 108 third rising and falling edges.
FIG. 1D represents the waveforms for various signals in the circuit 100 of FIG. 1A for fast operating conditions. As in FIGS. 1B and 1C, waveform 108 represents clock signal 108 and consists of a first rising edge 153 and a first falling edge and additional rising and falling edges, each occurring periodically with a delay T between each rising edge and an equivalent delay T between each falling edge where T is the clock period. Waveform 136 represents clock signal C2136 and consists of first rising edge 155 and first falling edge 157, followed by a logic low level 167 instead of the expected periodic clock pulses. Waveform 136 first rising edge 155 occurs xcfx84 time units after waveform 108 first rising edge 153 which places waveform 136 first rising edge 155 occurring after waveform 108 first rising edge 153 and before waveform 108 first falling edge. In FIG. 1D, xcfx84 is less than T.
Waveform 148 represents selector signal 148 and consists of first rising edge 159 occurring after waveform 136 first rising edge 155. Waveform 112 represents signal 112 provided by selector 110 and consists of first rising edge 161, first falling edge 163, followed by logic low level 165 instead of the expected periodic clock pulses. Waveform 112 first rising edge 161 occurs after waveform 108 first rising edge 153, but before waveform 108 first falling edge. Waveform 148 first rising edge 159 occurs after waveform 112 first rising edge 161 but before waveform 112 first falling edge 163 and before waveform 108 first falling edge.
The process of stopping the clock is initiated by the clock signal 108 rising edge 153 which propagates through selector 110 to form signal 112 rising edge 161 which continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 rising edge 155. Selector signal 148 is a logic low level which causes selector 110 to provide output signal 108 to signal 112. Clock signal C2136 rising edge 155 causes storage circuit 152 to provide rising edge 159 for selector signal 148. Selector signal 148 rising edge 159 occurs after clock signal 108 waveform 108 first rising edge 153 but prior to clock signal 108 waveform 108 first falling edge while clock signal 108 is a logic high level. Selector signal 148 logic high signal causes selector 110 to provide logic low level signal 142 to output signal 112, forming waveform 112 first falling edge 163 prior to clock signal 108 waveform 108 first falling edge. As a result, the clock pulse on signal 112 waveform 112 first rising edge 161 and first falling edge 163 is smaller than the clock pulse provided by signal 108 first waveform first rising edge 153 and first falling edge. Signal 112 waveform 112 first falling edge 163 continues to propagate through clock distribution elements 114, 118, 124, 128, and 132 causing clock C2136 waveform 136 first falling edge 157. As a result, the clock pulse on signal 136 waveform 136 first rising edge 155 and first falling edge 157 is smaller than the clock pulse provided by signal 108 waveform 108 first rising edge 153 and first falling edge. When clock signal 108 second rising edge occurs, selector circuit 110 does not provide clock signal 108 to signal 112 due to the logic high level provided by selector signal 148. Signal 112 remains at logic low level 165 instead of the expected periodic clock signal 108 second rising and falling edges. Signal 112 logic low level 165 keeps all clocks signals at a static logic level as represented by clock C2136 logic low level 167 instead of the expected periodic clock pulse from clock signal 108 second rising and falling edges.
In summary, circuit 100 of FIG. 1A has the following disadvantages as shown in FIGS. 1B, 1C, and 1D. When selector signal 148 in FIG. 1A changes from a logic low level to a logic high level, the clock signal C2136 in FIG. 1B representing the typical process delays, shown as the waveform 136 in FIG. 1B, has one clock pulse which is equivalent to the clock pulse of signal 108 waveform 108. When selector signal 148 of FIG. 1A changes from a logic low level to a logic high level, the clock signal 136 in FIG. 1C, representing the slow process delays, shown as waveform 136, has one clock pulse which is equivalent to the clock pulse of signal 108 waveform 108, and a second clock pulse formed by waveform 136 rising edge 139 and falling edge 147, smaller than the clock pulse of signal 108 waveform 108. When selector signal 148 of FIG. 1A changes from a logic low level to a logic high level, the clock signal C2136 in FIG. 1D, representing the fast process delays, shown as waveform 136, has one clock pulse which is smaller than the clock pulse of signal 108 waveform 108. Therefore, circuit 100 of FIG. 1A produces a non-determistic number of clock pulses and ill-formed clock pulses when selector signal 148 of FIG. 1A changes from a logic low level to a logic high level. Hence, it would be advantageous to have an improved method and apparatus for transferring data between two different clock domains which are both derived from the same clocking source.
The present invention provides a method and system for controlling a clock signal. The clock signal is first stored in a storage device. An input representing a clock control signal is input into a first end of a plurality of interconnected memory storage circuits. An outputted clock signal is output from a second end of the plurality of interconnected memory storage circuits based on receipt of the pulse representing the clock control signal. In one embodiment, the plurality of interconnected memory storage circuits is comprised of latches. In an alternate embodiment, the plurality of interconnected memory storage circuits is comprised of latches and master/slave flip-flops.